By Jairo Gutierrez, Koro Tawa
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Extra resources for Balancing Theoretical and Practical Goals in the Delivery of a University-Level Data Communications Program
In general, the if and else parts of each if-then-else statement ex ecute in parallel. For instance in lines 3–4, the processors participate (simultaneously) in a partitioning phase. In lines 6–7, where the enabled processors carry out the communication phase, processors of line 7 read the values written by processors of line 6. We also assume that if no processor writes to a bus, then reading from that bus into a variable does not alter the contents of that variable. 3 Fundamental Algorithmic Techniques In this section we present R-Mesh algorithms for problems on a wide array of topics including graphs, arithmetic, and sorting.
In Chapter 3, we describe model restrictions that favor implementability. Chapters 8 and 9 present simulations between various models that allow algorithms on less implementable models to be ported to a more implementable platform. In Chapter 11, we describe implementations of the segmentable bus and of a useful restriction of the R-Mesh. In the meanwhile, we will direct our discussion towards developing fundamental reconfiguration techniques and identifying approaches that lend themselves to a reasonable hardware implementation without get ting bogged down in details of hardware design and technological con straints.
Therefore, processor can use its identity and the level of recursion to determine whether or not to set switch This implies that no processor other than processor need have access to switch Similarly, for Illustration 2, the only information used to set switch is input bit once again, only processor need have access to switch This local control has the advantage of being simple, yet versatile as processors have “connection autonomy” or the ability to indepen dently configure connections (or switches) assigned to them.